| nSys Design Systems
Trainee Electronics Engineer
Experience: 0 - 2 Years
Compensation: Rupees 3,00,000
A great start with excellent growth prospects Job Description :
* Verification of ASIC Designs
* Development of Verification IPs
* Coding of Designs / Behavioral Models in Verilog and SystemVerilog
Desired Profile :
# Sound Digital Design Fundamentals is essential
# Knowledge of microprocessors is essential
# Knowledge of Verilog/VHDL is preferred
# Knowledge of C++ & OOPS concepts is preferred
# Excellent academic track record
# Excellent communication skills
Contact Details :
Name: Shilpa
nSys Design Systems
Email : hr(at)nsysinc.com
Reference : nSys_FE | 
No comments:
Post a Comment